1. Field of the Invention
The present invention relates in general to the field of signal processing, and more specifically, to a system and method for calibrating a redundant number system successive approximation analog-to-digital converter.
2. Description of the Related Art
Analog-to-digital converters (ADCs) convert analog signals into digital signals. ADCs find widespread use in many mixed signal applications. Converting analog audio signals into digital signals represents a common mixed signal application. Successive approximation register (SAR) ADCs represent a popular ADC technology particularly for medium to high resolution ADCs. Although the acronym “SAR” actually stands for Successive Approximation Register (the logic block that controls the conversion process), “SAR” is generally accepted as the acronym for the successive approximation analog-to-digital converter system itself.
FIG. 1 depicts a general SAR ADC 100 that converts an analog input signal Vin into a digital output signal y(n). In general, SAR ADC 100 receives the analog input signal Vin and employs a digital-to-analog converter (DAC) 101 and a comparator 106 to convert the analog input signal Vin into the digital output signal y(n). The DAC 101 includes an array of 16 converter reference elements CAP15, CAP14, . . . , CAP0 to develop a 16-bit conversion of the analog input signal Vin. The values of the converter reference elements can be represented by a sixteen element weight vector W with the most significant bit in the initial position. The SAR ADC 100 has a resolution equal to one-half of the value of the least significant bit. The number of converter reference elements in DAC 101 can be increased or decreased to respectively increase or decrease the resolution of the SAR ADC 100.
SAR ADC 100 uses charge redistribution to convert the analog input signal Vin into the digital output signal y(n). The 16 converter reference elements of CAP15, CAP14, . . . , CAP0 are capacitors although other embodiments of SAR ADC 100 can use resistors or other circuit element types. The SAR logic 102 generates a successive approximation converter reference element vector Cj where j is an updatable index reference. The values of vector Cj, {CAP15, CAP14, . . . , CAP0}, control the position of switches 104.15, 104.14, . . . , 104.0, 104.GND. SAR ADC 100 begins the conversion process by switching the most significant bit (MSB) switch 104.15 to the Vin node to charge the most significant bit (MSB) capacitor CAP15 to a value proportional to a voltage level of the analog input signal Vin. Switches for the remaining converter reference elements are set by vector Cj to connect to the VREF node to charge the remaining converter reference elements to reference voltage VREF, which provides a bipolar offset from the input voltage Vin. SAR logic 102 next updates the vector Cj to change the position of switches 104.15, 104.14, . . . , 104.0 and successively move the total trapped charge between each of the converter reference elements in DAC 101. Comparator 106 senses the voltage between the inverting (−) and non-inverting node (+) and provides a binary output that indicates which node has the higher voltage.
SAR logic 102 initially samples the analog input signal Vin by setting vector Cj so that each of switches 104.15, . . . , 104.0, 104. GND are connected to ground. The sampled analog input voltage Vin is held by setting vector Cj so that element CAP15 is connected to the reference voltage node VREF and the remaining elements are connected to ground GND. Switch 104.GND is then opened allowing the voltage at the inverting terminal of comparator 106 to move in accordance with the settings of switches 104.15, 104.14, . . . , 104.0. If all switches 104.15, 104.14, . . . , 104.0 are connected to the ground node GND, a voltage equal to −Vin appears at the inverting terminal of comparator 106. With CAP15 connected to ground, a voltage equal to voltage VREF divided by the ratio of the value of element CAP15 to the total of all values of the capacitors in the converter reference element array of DAC 101 appears at the inverting terminal of comparator 106. If the output of comparator is a logical 1, SAR logic 102 latches switch 104.15 to the reference voltage node VREF; otherwise SAR logic 102 latches switch 104.15 to the ground node GND. The process continues until the SAR logic 102 has cycled and set each of the switches 104.15, 104.14, . . . , 104.0.
Thus, during each move of the total trapped charge, the voltage at the comparator 106 inputs changes in accordance with the setting of switches 104.15, 104.14, . . . , 104.0. The SAR logic 102 detects the voltage output of comparator 106. The SAR logic 102 generates a vector Cj and sets each element {CAP15, CAP14, . . . , CAP0} of the vector Cj based upon the value of the current setting successive approximation converter reference element vector Cj and corresponding output of comparator 106. Thus, if switch 104.15 is 1, i.e. connected to voltage reference node VREF, and the output of comparator 106 is logical 1, then CAP15 is 1. In the next iteration, if switch 104.14 is then 1 and the output of comparator 106 is logical 0, then CAP14 is 0, and so on until SAR logic 102 determines each element of the vector Cj. SAR logic 102 determines the digital value of the analog input signal Vin by determining the dot product of an element weight vector W and converting the scalar result into a digital output value digital output signal y(n). In at least one embodiment, SAR ADC 100 is configured and operates as described in U.S. Pat. No. 6,844,840, “Successive-Approximation-Register (SAR) Analog-To-Digital Converter (ADC) and Method Utilizing N Three-Way Elements”, inventor John L. Melanson, assigned to Cirrus Logic, Inc., and issued Jun. 18, 2005, referred to herein as “Melanson Patent”. The Melanson Patent is hereby incorporated by reference in its entirety.
The weight vector W={CAP15, CAP14, . . . , CAP0}. The values of CAP15, CAP14, . . . , CAP0 can be based upon any radix. In one embodiment, a radix of 2 is used so that the weight vector W={CAP15, CAP15/(21), CAP15/(22), . . . , CAP15/(215)}. In other embodiments, a radix of less than 2 is used, such as a radix equal to 1.8 so that the weight vector W={CAP15, CAP15/(1.81), CAP15/(1.82), . . . , CAP15/(1.815)}. Other redundant number systems include binary number systems that include one or more repeating elements, for example {1, ½, ¼, ⅛, 1/16, 1/16, 1/32, 1/64, . . . }. The repeating elements are added to generate a desired amount of redundancy. In another embodiment, the additional elements do not have to be the same. For example, a binary sequence with inserted elements that are not power of 2 multiples can be used such as {1, ½, ¼, ⅛, 1/16, .75/16, 1/32, 1/64, . . . }.
As described in exemplary embodiments of U.S. Pat. No. 4,336,526, using a radix of less than two provides one embodiment of a redundant number system. Using a redundant number system provides overlap in the conversion process of SAR logic 102, thus, allowing for imprecision in the fabrication of the actual converter reference elements in DAC 101. U.S. Pat. No. 4,336,526, entitled “Successive Approximation Analog-to-Digital Converter Using Non-Binary Series”, inventor Basil Weir, and issued on Jun. 22, 1982, is hereby incorporated by reference in its entirety.
The converter reference elements of DAC 101 are generally fabricated as part of an integrated circuit. Although the values of converter reference elements are designed with specific values, the exact values of CAP15, CAP14, . . . , CAP0 are generally unknown.